--
-- CSSE2000 8 Bit Microprocessor
-- Copyright (C) 2011 Nathan Rossi (University of Queensland)
--
-- THIS DESIGN/CODE IS PROVIDED TO YOU UNDER THE FOLLOWING LICENSE:
--
-- All material is restricted to use in the CSSE2000 Project for 2011.
-- You may not redistribute the file/code/design, without the consent of the author.
--
-- DO NOT MODIFY THIS FILE
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;
use work.proc_package.ALL;

package proc_components is

	-- Processor Components
	component proc_top port (
		-- Control
		clk : in std_logic;
		rst : in std_logic;
		en : in std_logic;
		
		halt : in std_logic;
		
		-- Debug Port
		debug_reg_addr : in PROC_REG_ADDR_TYPE;
		debug_reg_wr_en : in std_logic;
		debug_reg_in : in PROC_REG_DATA_TYPE;
		debug_reg_out : out PROC_REG_DATA_TYPE;
		debug_pc_out : out PROC_PROG_ADDR_TYPE;
		debug_instruction : out PROC_PROG_DATA_TYPE;
		
		-- External Bus
		bus_out : in PROC_BUS_DATA_TYPE;
		bus_in : out PROC_BUS_DATA_TYPE;
		bus_addr : out PROC_BUS_ADDR_TYPE;
		bus_busy : in std_logic;
		bus_rdwr : out std_logic;
		bus_en : out std_logic;
		bus_rst : out std_logic;
		bus_clk : out std_logic;
		
		-- External Program Memory
		prog_mem_clk : out std_logic;
		prog_mem_en : out std_logic;
		prog_mem_addr : out PROC_PROG_ADDR_TYPE;
		prog_mem_data : in PROC_PROG_DATA_TYPE
	); end component;

	component proc_controlunit port (
		clk : in std_logic;
		rst : in std_logic;
		en : in std_logic;
		
		-- Instruction
		instruction : in PROC_PROG_DATA_TYPE;
		
		-- Immediate Bus Output
		immediate_value : out PROC_REG_DATA_TYPE;
		
		-- Register File Control
		register_en : out std_logic;
		register_p_0_write : out std_logic;
		register_p_0_write_source : out PROC_MUX_SOURCE;
		register_p_0_addr_direct : out PROC_REG_ADDR_TYPE;
		register_p_1_addr_direct : out PROC_REG_ADDR_TYPE;
		
		-- ALU Control
		alu_en : out std_logic;
		alu_b_source : out PROC_MUX_SOURCE;
		alu_mode : out PROC_ALU_MODE;
		
		-- Program Counter Control
		pc_en : out std_logic;
		pc_jump_source : out PROC_MUX_SOURCE;
		pc_mode : out PROC_PC_MODE;
		
		-- Status Register Control
		sreg_en : out std_logic;
		sreg_source : out PROC_MUX_SOURCE;
		
		-- Status Register Bit Manipulator Control
		sreg_bit_en : out std_logic;
		sreg_bit_index : out PROC_REG_BIT_INDEX_TYPE;
		sreg_bit_value_in : out std_logic;
		sreg_jump_en : out std_logic;
		
		-- Memory Controller Control
		mem_en : out std_logic;
		mem_addr_source : out PROC_MUX_SOURCE
	); end component;

	component proc_bitmanipulator port (
		rst : in std_logic;
		clk : in std_logic;
		en : in std_logic;
		
		value_in : in PROC_REG_DATA_TYPE;
		value_out : out PROC_REG_DATA_TYPE;
		
		bit_index : in PROC_REG_BIT_INDEX_TYPE;
		bit_in : in std_logic;
		bit_eq : out std_logic
	); end component;

	component proc_sreg port (
		rst : in std_logic;
		clk : in std_logic;
		en : in std_logic;
		
		input : in PROC_REG_DATA_TYPE;
		output : out PROC_REG_DATA_TYPE
	); end component;

	component proc_registers port (
		clk : in std_logic;
		rst : in std_logic;
		en : in std_logic;
		
		-- Port 0
		p_0_wr_en : in std_logic;
		p_0_addr : in PROC_REG_ADDR_TYPE;
		p_0_datain : in PROC_REG_DATA_TYPE;
		p_0_dataout : out PROC_REG_DATA_TYPE;
		
		-- Port 1
		p_1_addr : in PROC_REG_ADDR_TYPE;
		p_1_dataout : out PROC_REG_DATA_TYPE
	); end component;

	component proc_instructionfetcher port (
		clk : in std_logic;
		en : in std_logic;
		
		addr : in PROC_PROG_ADDR_TYPE;
		value : out PROC_PROG_DATA_TYPE;
		
		-- External Memory Signals
		prog_mem_clk : out std_logic;
		prog_mem_en : out std_logic;
		prog_mem_addr : out PROC_PROG_ADDR_TYPE;
		prog_mem_data : in PROC_PROG_DATA_TYPE
	); end component;

	component proc_instructionfetcher_rom generic (
		ROM_CONTENTS : ROM_FILE_TYPE := (others => (others => '0'))
	); port (
		clk : in std_logic;
		rst : in std_logic;
		en : in std_logic;
		
		addr : in PROC_PROG_ADDR_TYPE;
		value : out PROC_PROG_DATA_TYPE
	); end component;
	
	component proc_progcounter port (
		clk : in std_logic;
		rst : in std_logic;
		en : in std_logic;
		
		mode : in PROC_PC_MODE;
		
		value_in : in PROC_PROG_ADDR_TYPE;
		value_out : out PROC_PROG_ADDR_TYPE
	); end component;

	component proc_alu port (
		clk : in std_logic;
		rst : in std_logic;
		en : in std_logic;
		
		mode : in PROC_ALU_MODE;
		
		-- Inputs
		status_in : in PROC_REG_DATA_TYPE;
		a : in PROC_REG_DATA_TYPE;
		b : in PROC_REG_DATA_TYPE;
		
		-- Outputs
		result : out PROC_REG_DATA_TYPE;
		status_out : out PROC_REG_DATA_TYPE
	); end component;

	-- Other Components
	component mem_block port (
		-- Port A
		a_clk : in std_logic;
		a_en : in std_logic;
		a_wr_en : in std_logic;
		a_addr : in std_logic_vector(8 downto 0);
		a_in : in std_logic_vector(15 downto 0);
		a_out : out std_logic_vector(15 downto 0);
		
		-- Port B
		b_clk : in std_logic;
		b_en : in std_logic;
		b_wr_en : in std_logic;
		b_addr : in std_logic_vector(8 downto 0);
		b_in : in std_logic_vector(15 downto 0);
		b_out : out std_logic_vector(15 downto 0)
	); end component;
end proc_components;

package body proc_components is   
end proc_components;
